Alarm Lock PL6500 User's Guide download pdf (Page 36)

Chelsea Technologies Group

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User Guide HB179 Issue 7.0

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The flash duration (options 9 and D) is programmed in instrument units corresponding to clock

cycles in the FPGA, as integers ranging from 4 to 100. The minimum value is set to 4 which

gives a flash duration of 1.1µs, this being above 1 µs, which is the design specification for the

detector electronics. Each additional integer increases in the flash duration value will increase

the flash duration time by 60 ns.

Therefore period = (1.1 + (x - 4) * 0.06) µs.

The interflash delay (options A and E) is programmed in instrument units corresponding to a

software clock separating the request for each flash. When an individual flash is generated, the

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programs the FPGA hardware counter to deliver a flash of width described by the

flash duration value, then it enters a software loop to await the start of the next flash. The range of

programmable values are from 0 (no wait; just overhead time) to 1000. An input value of 0

corresponds to a delay of 2.8 µs and integer increases in interflash delay will increase the flash

period in steps of 800 ns.

The time between the last saturation flash and the first decay flash is the sum of the saturation

interflash delay and decay interflash delay. Subsequent delay flashes are then separated by the

programmed decay interflash delay time.

5.4 INTERNAL DATA HANDLING AND ANALYSIS

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uses a high speed FPGA logic circuit to read video-speed A/D converters which

monitor the observed signal from both the photomultiplier fluorescence detector and photodiode

excitation detector. These signals are digitised every 125 nanoseconds during a flash

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Alarm Lock PL6500 User's Guide Page 36